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3.4 Division 본문
A Division Algorithm and Hardware

The 32-bit Quotient register set to 0.
Each iteration of the algorithm needs to move the divisor to the right one digit, so we start with the divisor placed in the left half of the 64-bit Divisor register and shift it right 1 bit each step to align it with the dividend.
The Remainder register is initialized with the dividend.

Example)
Using a 4-bit version of the algorithm to save pages, let’s try dividing 7ten by 2ten, or 0000 0111two by 0010two.
Answer)
The Divisor register, ALU, and Quotient register are all 32 bits wide, with only the Remainder register left at 64 bits.
Comparing with first version of ALU and Divisor registers are halved and the remainder is shifted left.
This version also combines the Quotient register with the right half of the Remainder register.
Signed Division
The simplest solution is to remember the signs of the divisor and dividend and then negate the quotient if the signs disagree.

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